1. Field of the Invention
This invention relates to a semiconductor memory device, a control method for the semiconductor memory device, and a memory card including the semiconductor memory device. More particularly, this invention relates to a nonvolatile semiconductor memory device including MOS transistors, each having a floating gate and a control gate.
2. Description of the Related Art
NOR flash memories and NAND flash memories have been widely used as nonvolatile semiconductor memories.
In recent years, a flash memory combining the features of the NOR flash memory and the NAND flash memory has been proposed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. A flash memory of this type has memory cells, each including two MOS transistors (hereinafter, a flash memory including such memory cells is referred to as a 2Tr flash memory). In a memory cell of a 2Tr flash memory, one MOS transistor functioning as a nonvolatile memory section has a structure including a control gate and a floating gate and is connected to a bit line. The other MOS transistor, which is connected to a source line, is used to select a memory cell.
In flash memories, when the voltages of the word lines and others are reset at the end of a write, read, or erase operation, an adverse effect of coupling must be taken into consideration. Related techniques have been described in, for example, U.S. Pat. No. 6,373,749 and in Shigeru Atsumi et al., “A Channel-Erasing 1.8-V-Only 32 Mb NOR Flash EEPROM with a Bit-Line Direct-Sensing Scheme,” IEEE International Solid-State Circuits Conference/SESSION 16/NON-VOLATILE and SRAM/PAPER TP 16.7, February, 2000.